ylai@lemmy.ml to

RISC-V@lemmy.mlEnglish · 8 months ago

Edge AI chiplet uses SemiDynamics RISC-V cores

www.eenewseurope.com

0

1

Edge AI chiplet uses SemiDynamics RISC-V cores

www.eenewseurope.com

ylai@lemmy.ml to

RISC-V@lemmy.mlEnglish · 8 months ago

0

YorChip is developing a 12nm edge AI chiplet design that will be under 25 sq mm using RISC-V cores from Semidynamics in Barcelona.

You must log in or register to comment.

Chat

RISC-V@lemmy.ml

You are not logged in. However you can subscribe from another Fediverse account, for example Lemmy or Mastodon. To do this, paste the following into the search field of your instance: !riscv@lemmy.ml

RISC-V (pronounced “risk-five”) is a license-free, modular, extensible instruction set architecture (ISA).

Youtube | Twitter

Other RISC-V communities on Lemmy

Visibility: Public

This community can be federated to other instances and be posted/commented in by their users.

1 user / day
1 user / week
1 user / month
1 user / 6 months
0 local subscribers
692 subscribers
61 Posts
0 Comments
Modlog

mods:
testman@lemmy.ml